KeblaOS

CPU Registers

System : Architecture : x86, Bit : 64

In x86-64 architecture, registers are small, fast storage locations within the CPU that are used to hold data, addresses, and control information. The x86-64 architecture extends the 32-bit x86 architecture by providing more registers and increasing their size to 64 bits. Here are the main types of registers and their uses:

1. General-Purpose Registers (GPRs)

These registers are used for a variety of purposes, including arithmetic, logic operations, and data movement. In x86-64, there are 16 general-purpose registers, each 64 bits wide. They can be accessed in different sizes:

• 64-bit (R): RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, R8-R15
• 32-bit (E): EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP, R8D-R15D
• 16-bit (no prefix): AX, BX, CX, DX, SI, DI, BP, SP, R8W-R15W
• 8-bit (H/L): AH, AL, BH, BL, CH, CL, DH, DL, SIL, DIL, BPL, SPL, R8B-R15B

Common Uses:

• RAX/EAX/AX/AH/AL: Accumulator register, used for arithmetic operations, return values from functions.
• RBX/EBX/BX/BH/BL: Base register, often used as a pointer to data.
• RCX/ECX/CX/CH/CL: Counter register, used in loop operations.
• RDX/EDX/DX/DH/DL: Data register, used in I/O operations and some arithmetic operations.
• RSI/ESI/SI/SIL: Source Index register, used as a pointer to a source in stream operations.
• RDI/EDI/DI/DIL: Destination Index register, used as a pointer to a destination in stream operations.
• RBP/EBP/BP/BPL: Base Pointer register, used to point to the base of the stack frame.
• RSP/ESP/SP/SPL: Stack Pointer register, used to point to the top of the stack.
• R8-R15: Additional general-purpose registers introduced in x86-64, used for various purposes.

2. Segment Registers

These registers are used to segment memory and are primarily used in legacy 16-bit and 32-bit modes. In 64-bit mode, their use is limited.

• CS: Code Segment, points to the segment containing the current instruction.
• DS: Data Segment, points to the segment containing most data.
• SS: Stack Segment, points to the segment containing the stack.
• ES, FS, GS: Extra Segment registers, used for additional data segments.

Common Uses:

• CS: Used to manage the code segment.
• DS: Used to manage the data segment.
• SS: Used to manage the stack segment.
• FS, GS: Often used for thread-local storage in modern operating systems.

3. Instruction Pointer (RIP/EIP/IP)

This register holds the address of the next instruction to be executed.

• RIP: 64-bit instruction pointer.
• EIP: 32-bit instruction pointer.
• IP: 16-bit instruction pointer.

Common Uses:

• RIP/EIP/IP: Used to control the flow of execution by pointing to the next instruction.

4. Flags Register (RFLAGS/EFLAGS/FLAGS)

This register contains status and control flags that affect the operation of the CPU.

• RFLAGS: 64-bit flags register.
• EFLAGS: 32-bit flags register.
• FLAGS: 16-bit flags register.

Common Flags:

• CF: Carry Flag, indicates an overflow or underflow in arithmetic operations.
• ZF: Zero Flag, set if the result of an operation is zero.
• SF: Sign Flag, set if the result of an operation is negative.
• OF: Overflow Flag, indicates an overflow in signed arithmetic.
• PF: Parity Flag, indicates the parity of the result.
• AF: Auxiliary Carry Flag, used in BCD arithmetic.
• DF: Direction Flag, controls the direction of string operations.
• IF: Interrupt Enable Flag, enables or disables interrupts.
• TF: Trap Flag, used for single-step debugging.

5. Floating-Point Registers (XMM, YMM, ZMM)

These registers are used for floating-point and SIMD (Single Instruction, Multiple Data) operations.

• XMM0-XMM15: 128-bit registers used for SSE (Streaming SIMD Extensions) operations.
• YMM0-YMM15: 256-bit registers used for AVX (Advanced Vector Extensions) operations.
• ZMM0-ZMM31: 512-bit registers used for AVX-512 operations.

Common Uses:

• XMM/YMM/ZMM: Used for high-performance floating-point and vectorized computations.

6. Control Registers

These registers control the operation of the CPU and are used in system-level programming.

• CR0: Contains system control flags, such as paging and protected mode.
• CR1: Reserved.
• CR2: Contains the page-fault linear address.
• CR3: Contains the base address of the page directory.
• CR4: Contains additional system control flags, such as enabling SSE or virtualization.

Common Uses:

• CR0: Controls CPU modes and features.
• CR2: Used in handling page faults.
• CR3: Used in memory management.
• CR4: Enables advanced CPU features.

7. Debug Registers

These registers are used for debugging purposes.

• DR0-DR7: Used to set breakpoints and control debugging features.

Common Uses:

• DR0-DR3: Hold breakpoint addresses.
• DR6: Debug status register.
• DR7: Debug control register.

8. Model-Specific Registers (MSRs)

These registers are used for CPU-specific features and are accessed using special instructions like RDMSR and WRMSR.

Common Uses:

• MSRs: Used for performance monitoring, power management, and other CPU-specific features.

Summary

• General-Purpose Registers: Used for arithmetic, logic, and data movement.
• Segment Registers: Used in legacy modes for memory segmentation.
• Instruction Pointer: Points to the next instruction to execute.
• Flags Register: Contains status and control flags.
• Floating-Point Registers: Used for floating-point and SIMD operations.
• Control Registers: Control CPU operation and system-level features.
• Debug Registers: Used for debugging purposes.
• Model-Specific Registers: Used for CPU-specific features.

Understanding these registers and their uses is crucial for low-level programming, such as writing assembly language code or developing operating systems.

For my KeblaOS I have define the following structure to manage cpu state

struct registers { // Total 26*8 = 208 bytes, 16 bytes aligned
    // Segment registers
    uint64_t gs;            // Offset 8*0
    uint64_t fs;            // Offset 8*1
    uint64_t es;            // Offset 8*2
    uint64_t ds;            // Offset 8*3

    // General purpose registers
    uint64_t rax;           // Offset 8*4
    uint64_t rbx;           // Offset 8*5
    uint64_t rcx;           // Offset 8*6
    uint64_t rdx;           // Offset 8*7
    uint64_t rbp;           // Offset 8*8
    uint64_t rdi;           // Offset 8*9
    uint64_t rsi;           // Offset 8*10
    uint64_t r8;            // Offset 8*11
    uint64_t r9;            // Offset 8*12
    uint64_t r10;           // Offset 8*13
    uint64_t r11;           // Offset 8*14
    uint64_t r12;           // Offset 8*15
    uint64_t r13;           // Offset 8*16
    uint64_t r14;           // Offset 8*17
    uint64_t r15;           // Offset 8*18

    uint64_t int_no;        // Offset 8*19
    uint64_t err_code;      // Offset 8*20

    // Interrupt return CPU state registers value
    uint64_t iret_rip;      // Offset 8*21
    uint64_t iret_cs;       // Offset 8*22
    uint64_t iret_rflags;   // Offset 8*23
    uint64_t iret_rsp;      // Offset 8*24
    uint64_t iret_ss;       // Offset 8*25
    
} __attribute__((packed));
typedef struct registers registers_t;

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